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19-2541; Rev 0; 7/02
1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs
General Description
The MAX9310 is a fast, low-skew 1:5 differential driver with selectable LVPECL/HSTL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 345ps with 45.5mA of supply current. The MAX9310 operates from a 2.375V to 2.625V power supply for use in 2.5V systems. A 2:1 input multiplexer is used to select one of two differential inputs. The input selection is controlled through the CLKSEL pin. This device also features a synchronous enable function. The MAX9310 is offered in a space-saving 20-pin TSSOP package and operates over the extended temperature range from -40C to +85C. o 8ps Output-to-Output Skew o 345ps Propagation Delay o Accepts LVPECL and Differential HSTL Inputs o Synchronous Output Enable/Disable o Two Selectable Differential Inputs o 2.375V to 2.625V Supply Voltage o ESD Protection: 2kV (Human Body Model) o Input Bias Resistors Drive Output Low for Open Inputs
Features
o Guaranteed 1.0GHz Operating Frequency
MAX9310
Applications
Data and Clock Drivers and Buffers Central-Office Backplane Clock Distribution DSLAM Base Stations ATE
Ordering Information
PART MAX9310EUP TEMP RANGE -40C to +85C PIN-PACKAGE 20 TSSOP
Functional diagram appears at end of data sheet.
Pin Configuration
TOP VIEW
Typical Application Circuit
Q0 1 QO 2 Q1 3 Q1 4
20 VCC 19 EN 18 VCC 17 CLK1
MAX9310
ZO = 50 Q_
RECEIVER
Q2 5 Q2 6 Q3 7
MAX9310
16 CLK1 15 I.C. 14 CLK0 13 CLK0 12 CLKSEL 11 GND
ZO = 50 Q_
100
Q3 8 Q4 9 Q4 10
TSSOP
________________________________________________________________ Maxim Integrated Products
1
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1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs MAX9310
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.1V EN, CLKSEL, CLK_, CLK_, to GND............-0.3V to (VCC + 0.3V) CLK_ to CLK_ ...........................................................|VCC - GND| Continuous Output Current .................................................24mA Surge Output Current..........................................................50mA Continuous Power Dissipation (TA = +70C) Single-Layer PC Board 20-Pin TSSOP (derate 7.69mW/C above +70C) ......615mW Multilayer PC Board 20-Pin TSSOP (derate 11mW/C above +70C) .........879mW Junction-to-Ambient Thermal Resistance in Still Air Single-Layer PC Board 20-Pin TSSOP .........................................................+130C/W Multilayer PC Board 20-Pin TSSOP ...........................................................+91C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow Single-Layer PC board 20-Pin TSSOP ...........................................................+96C/W Junction-to-Case Thermal Resistance 20-Pin TSSOP ...........................................................+20C/W Operating Temperature Range .......................... -40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (inputs and outputs) .......................2kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - GND = 2.375V to 2.625V, outputs terminated with 100 1%, unless otherwise noted. Typical values are at VCC - GND = 2.5V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
SINGLE-ENDED INPUTS (CLKSEL, EN) Input High Voltage Input Low Voltage Input Current VIH VIL IIN VIH(MAX), VIL(MAX) VCC 1.165 VCC 1.81 -150 VCC 0.88 VCC 1.475 +50 VCC 1.165 VCC 1.81 -150 VCC 0.88 VCC 1.475 +50 VCC 1.165 VCC 1.81 -150 VCC 0.88 VCC 1.475 +50 V V A
DIFFERENTIAL INPUTS (CLK_, CLK_) Differential Input High Voltage Differential Input Low Voltage Differential Input Voltage Input Current OUTPUTS (Q_, Q_) Output High Voltage Output Low Voltage Differential Output Voltage VOH VOL VOD Figure 1 Figure 1 VOH - VOL, Figure 1 0.9 250 350 450 1.6 0.9 250 350 450 1.6 0.9 250 350 450 1.6 V V mV VIHD VILD VID IIH, IIL Figure 1 Figure 1 VIHD - VILD CLK_, or CLK_ = VIHD or VILD 1.2 GND 0.095 -60 VCC VCC 0.095 VCC +50 1.2 GND 0.095 -60 VCC VCC 0.095 VCC +50 1.2 GND 0.095 -60 VCC VCC 0.095 VCC +60 V V V A
2
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1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - GND = 2.375V to 2.625V, outputs terminated with 100 1%, unless otherwise noted. Typical values are at VCC - GND = 2.5V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER Change in VOD Between Complementary Output States Output Offset Voltage Change in VOS Between Complementary Output States Output ShortCircuit Current POWER SUPPLY Power-Supply Current ICC (Note 4) 42 75 45.5 75 48.5 75 mA SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
MAX9310
VOD
40
40
40
mV
VOS
1.125
1.25
1.375
1.125
1.25
1.375
1.125
1.25
1.375
mV
VOCM
25
25
25
mV
Q_ shorted to Q_ IOSC Q_ or Q_ shorted to GND
12 28
12 28
12 mA 28
AC ELECTRICAL CHARACTERISTICS
(VCC - GND = 2.375V to 2.625V, outputs terminated with 100 1%, fIN 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted. Typical values are at VCC - GND = 2.5V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 5)
PARAMETER Propagation Delay CLK_, CLK_ to Q_, Q_ Output-toOutput Skew Part-to-Part Skew Added Random Jitter Added Deterministic Jitter SYMBOL tPHL, tPLH tSKOO tSKPP CONDITIONS -40C MIN 250 TYP 335 MAX 600 MIN 250 +25C TYP 345 MAX 600 MIN 250 +85C TYP 345 MAX 600 UNITS
Figure 1
ps
(Note 6) (Note 7) fIN = 1.0GHz, clock pattern (Note 8) fIN = 1.0Gsps, 223 - 1 PRBS pattern (Note 8)
10
25 145
8
25 145
5
25 145
ps ps ps (RMS)
tRJ
0.4
1.0
0.4
1.0
0.4
1.0
tDJ
41
52
41
52
41
52
ps (P-P)
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1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs MAX9310
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC - GND = 2.375V to 2.625V, outputs terminated with 100 1%, fIN 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted. Typical values are at VCC - GND = 2.5V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 5)
PARAMETER Operating Frequency Differential Output Rise/Fall Time SYMBOL fMAX CONDITIONS VOD 250mV 20% to 80%, Figure 1 -40C MIN 1.0 TYP MAX MIN 1.0 +25C TYP MAX MIN 1.0 +85C TYP MAX UNITS GHz
tR/tF
140
205
300
140
205
300
140
205
300
ps
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25C. DC limits are guaranteed by design and characterized over the full operating temperature range. Note 4: All pins are open except VCC and GND, all outputs are loaded with 100 differentially. Note 5: Guaranteed by design and characterization. Limits are set to 6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 8: Device jitter added to the input signal.
Typical Operating Characteristics
(VCC - GND = 2.5V, outputs terminated with 100 1%, fIN = 1.0GHz, input transition time = 125ps (20% to 80%),VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.)
DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. FREQUENCY
MAX9310 toc01 MAX9310 toc02
SUPPLY CURRENT vs. TEMPERATURE
50 49 48 SUPPLY CURRENT (mA) 47 46 45 44 43 42 41 40 -40 -15 10 35 60 85 TEMPERATURE (C) ALL PINS ARE OPEN EXCEPT VCC AND GND OUTPUTS LOADED WITH 100 DIFFERENTIAL DIFFERENTIAL OUTPUT VOLTAGE (mV)
OUTPUT RISE/FALL vs. TEMPERATURE
fIN = 500MHz 215
MAX9310 toc03
450 400 350 300 250 200 150 100 50 0 0.25 0.50 0.75 1.00 1.25 1.50
220
RISE/FALL TIME (ps)
210 tF 205 tR
200 1.75 -40 -15 10 35 60 85 FREQUENCY (GHz) TEMPERATURE (C)
4
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1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs MAX9310
Typical Operating Characteristics (continued)
(VCC - GND = 2.5V, outputs terminated with 100 1%, fIN = 1.0GHz, input transition time = 125ps (20% to 80%),VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT (VIHD)
MAX9310 toc04
PROPAGATION DELAY vs. TEMPERATURE
MAX9310 toc05
390
400
PROPAGATION DELAY (ps)
350
PROPAGATION DELAY (ps) 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
370
380
360
330
340
310
320
290 VIHD (V)
300 -40 -15 10 35 60 85 TEMPERATURE (C)
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 NAME Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 GND CLKSEL CLK0 CLK0 I.C. CLK1 CLK1 FUNCTION Noninverting Differential Output 0. Typically terminated with 100 to Q0. Inverting Differential Output 0. Typically terminated with 100 to Q0. Noninverting Differential Output 1. Typically terminated with 100 to Q1. Inverting Differential Output 1. Typically terminated with 100 to Q1. Noninverting Differential Output 2. Typically terminated with 100 to Q2. Inverting Differential Output 2. Typically terminated with 100 to Q2. Noninverting Differential Output 3. Typically terminated with 100 to Q3. Inverting Differential Output 3. Typically terminated with 100 to Q3. Noninverting Differential Output 4. Typically terminated with 100 to Q4. Inverting Differential Output 4. Typically terminated with 100 to Q4. Ground Clock Select Input. Drive low to select the CLK0, CLK0 input. Drive high to select the CLK1, CLK1 input. Internal 60k pulldown to GND. Noninverting Differential Clock Input 0. Internal 75k pulldown to GND. Inverting Differential Clock Input 0. Internal 75k pullup to VCC and 75k pulldown to GND. Internally Connect. Do not connect externally. Noninverting Differential Input 1. Internal 75k pulldown to GND. Inverting Differential Input 1. Internal 75k pullup to VCC and 75k pulldown to GND.
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5
1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs MAX9310
Pin Description (continued)
PIN 18, 20 NAME VCC FUNCTION Positive Supply Voltage. Bypass each VCC to GND with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected clock input when EN is low. Outputs are synchronously driven to a differential low state on the falling edge of the selected clock input when EN is high. Internal 60k pulldown to GND (Figure 2).
19
EN
CLK VIHD - VILD CLK
VIHD
VILD
tPLHD
tPHLD
Q_ VOH - VOL Q_
VOH
VOL
80% 0V (DIFFERENTIAL) 20% Q_ - Q_ tR
80% 0V (DIFFERENTIAL) 20%
tF
Figure 1. MAX9310 Timing Diagram
EN tS tH tS tH
CLK CLK Q_ Q_ tS = SETUP TIME tH = HOLD TIME
tPLHD OUTPUTS ARE LOW OUTPUTS STAY LOW
Figure 2. MAX9310 EN Timing Diagram 6 _______________________________________________________________________________________
1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs
Detailed Description
The MAX9310 is a low-skew 1:5 differential driver with two selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. The selected clock accepts a differential input signal and reproduces it on five separate differential LVDS outputs. The inputs are biased with internal resistors such that the output is differential low when inputs are open. The output drivers are guaranteed to operate at frequencies up to 1.0GHz with LVDS output levels conforming to the EIA/TIA-644 standard. The MAX9310 is designed for 2.375V to 2.625V operation in systems with a nominal 2.5V supply.
Differential LVDS Output
The LVDS outputs must be terminated with 100 across Q_ and Q_, as shown in the Typical Application Circuit. The outputs are short-circuit protected.
MAX9310
Applications Information
Supply Bypassing
Bypass each VCC to GND with high-frequency surfacemount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance and reduce power-supply bounce with high-current transients.
Differential LVPECL Input
The MAX9310 has two input differential pairs that accept differential LVPECL/HSTL inputs. Each differential input pair has to be independently terminated. A select pin (CLKSEL) is used to activate the desired input. The maximum magnitude of the differential signal applied to the input is VCC. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (V IHD - VILD) apply simultaneously.
Controlled-Impedance Traces
Input and output trace characteristics affect the performance of the MAX9310. Connect high-frequency input and output signals to 50 characteristic impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces.
Output Termination
Terminate the outputs with 100 across Q_ and Q_, as shown in the Typical Application Circuit.
Synchronous Enable
The MAX9310 is synchronously enabled and disabled with outputs in a differential low state to eliminate shortened clock pulses. EN is connected to the input of an edge-triggered D flip-flop. After power-up, drive EN low and toggle the selected clock input to enable the outputs. The outputs are enabled on the falling edge of the selected clock input after EN goes low. The outputs are set to a differential low state on the falling edge of the selected clock input after EN goes high (Figure 2).
Chip Information
TRANSISTOR COUNT: 716 PROCESS: Bipolar
Input Bias Resistors
Internal biasing resistors ensure a (differential) output low condition in the event that the inputs are not connected. The inverting input (CLK_) is biased with a 75k pulldown to GND and a 75k pullup to VCC. The noninverting input (CLK_) is biased with a 75k pulldown to GND.
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7
1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs MAX9310
Functional Diagram
VCC
Q0
75k CLK0
Q0
Q1 CLK0 Q1 75k 75k Q2 0 VCC Q2
GND
GND
75k CLK1
1
Q3
Q3 CLK1 Q4 75k 75k Q4 GND CLKSEL Q EN I.C. D 60k GND GND
60k GND
MAX9310
8
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1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP,NO PADS.EPS
MAX9310
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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